Memory devices comprise a vast number of bitcells within which information is stored. In an example, a dual port bitcell array comprises dual port bitcells that are individually constructed from 8 transistors. A dual port bitcell comprises two ports that operate independently of one another, such that a first port performs read/write operations independently of a second port performing read/write operations. Because the first port and the second port operate in parallel, operation disturbs arise where a first operation on the first port, such as a write operation, and a second operation on the second port, such as a read operation, result in a collision that would otherwise cause data inconsistencies if allowed. Because the dual port bitcell comprises 8 transistors, the dual port bitcell occupies a relatively large amount of area resulting in area penalty for the memory device.